1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device and a depletion-type MOS transistor included in non-volatile semiconductor devices and the like.
2. Description of the Related Art
Conventionally, a non-volatile semiconductor memory device enabling electrical rewriting is known as one kind of semiconductor memory devices. Among such non-volatile semiconductor memory devices, a NAND flash memory including NAND cell blocks with a plurality of memory cells connected in series is widely used, since it has a high level of integration.
A memory cell formed in the NAND flash memory has a MOSFET structure in which a floating gate (charge accumulation layer) and a control gate are layered on a semiconductor substrate via an insulating film. A plurality of memory cells are connected in series, and neighboring cells share a source and a drain to form a NAND cell unit. A NAND cell unit is connected to the bit line as a single unit. This kind of NAND cell is arranged as a matrix to constitute a memory cell array. The memory cell array is integratedly formed on a p type semiconductor substrate or in a p type well region.
In a NAND flash memory, a voltage higher than the power supply voltage must be transferred to the control gate line in the selected block. In order to transfer this kind of high voltage to the memory cell, a conventional NAND flash memory is equipped with a row decoder circuit including a voltage conversion circuit that converts the power supply voltage into this kind of high voltage (see, for example, JP 2006-196061 A). Such a row decoder generally includes plural kinds of MOS transistors such as: an enhancement-type (E-type) n-channel MOS transistor with high-breakdown voltage; depletion-type (D-type) n-channel MOS transistors with high-breakdown voltage; and E-type p-channel MOS transistors with high breakdown-voltage.
Conventionally, on forming such MOS transistors, a channel implantation that implants impurities into the channel portion is carried out to adjust the threshold voltage. P-type impurities such as boron (B) and the like are used in the channel implantation of E-type n-channel MOS transistors. On the other hand, in the channel implantation of D-type n-channel MOS transistors, the n type impurity such as arsenic (As) is used. When such n type impurity is injected/implanted into areas including the region where the source-drain diffusion region is to be formed, the diffusion layer resistance of the source-drain diffusion regions formed later becomes lower, and so-called soft breakdown may occur in the transistor. This phenomenon is regarded as a problem.
In addition, a surface breakdown voltage of a transistor is generally classified into two kinds of voltages. One of them is called “intrinsic breakdown voltage” by which a transistor is completely destroyed. The other is called “soft breakdown voltage” by which a leakage current increases. The intrinsic breakdown voltage is higher than the soft breakdown voltage.
The voltage applied to a source, a drain and a gate of a transistor differs according to the types (E-type or D-type, n-channel or p-channel) and application purpose or usage of the transistor.
Depending on the application of the transistor, in some cases it is required that the soft breakdown voltage be high while the intrinsic breakdown voltage may be low, and vice-versa.
However, the intrinsic breakdown voltage is higher than the soft breakdown voltage. Thus, if attempting to obtain a high soft breakdown voltage, it is necessary to enlarge the entire area of the transistor. As a result there has been a problem that the chip area occupied by peripheral circuits becomes larger.